FAUTO=MANUAL, FIE=DISABLED, FSAFE=NORMAL, FLVL=LOGIC_0
Fault Control Register
| FIE | Fault Interrupt Enables 0 (DISABLED): FAULTx CPU interrupt requests disabled. 1 (ENABLED): FAULTx CPU interrupt requests enabled. |
| FSAFE | Fault Safety Mode 0 (NORMAL): Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). 1 (SAFE): Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. |
| FAUTO | Automatic Fault Clearing 0 (MANUAL): Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the states of FSTS[FHALF] and FSTS[FFULL]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL[FSAFE]. 1 (AUTOMATIC): Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. |
| FLVL | Fault Level 0 (LOGIC_0): A logic 0 on the fault input indicates a fault condition. 1 (LOGIC_1): A logic 1 on the fault input indicates a fault condition. |